New and analytical portal "hour of electronics". How to program FPGA on SystemVerilog Apply the design of great fpga projects

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PLIS (Programmed Logic Integrated Circuit) - a circuit integrated circuit, recognized for inducing digital languages ​​with a description of my special programming. Otherwise, it seems, FPGA is a chip, it’s good to take revenge on your own for a bunch of elements on the 74HCxx kshtalt. Like the most will be logical elements, like between them there will be links, and like links will be a scheme zvishnіshnіm svіtom, Indicated at the stage of FPGA programming.

Note: For now, in Russian language, on this day, the terms FPGA and FPGA (Field-Programmable Gate Array, Programmed by Koristuvach Gate Matrix) are accepted as interchangeable, which will be given behind the text. Prote varto know about the basis of that alternative point to the gap, zgіdno with any FPGA (FPGA) є one of the different PLIS (PLD, Programmable Logic Device).

Basic information about FPGA

For programming the FPGA, the Movie Hardware Description Language (HDL, Hardware Description Language) is written. Among them, the most popular are Verilog (that yoga dialect, SystemVerilog code), as well as VHDL. The movie is rich in many ways, but it has different syntax and differs in some details. Just as Verilog is such a C world description of equipment, then VHDL is obviously Pascal. Somewhat less popular, VHDL is less popular, but it is based on yogo richness compared to Verilog. 3 VHDL advantages (otherwise nedolіkіv, to whom yak) can be called strictly static typing. Verilog can sometimes implicitly cast types. In order to continue the analogy with C and Pascal, the movies are not so strong, so as not to take offense.

At the moment, the leading FPGA builders are Altera (together with Intel) and Xilinx. For the information of the various dzherels, at once the stench is controlled by at least 80% of the market. Three of the other gravels include Actel (purchased by Microsemi), Lattice Semiconductor, Quicklogic and SiliconBlue. From the entrance to Xilinx, you can only work from the middle of the opening to the Xilinx (called Vivado), and the middle of the opening to the Altra (called Quartus) can only be done from the middle of the opening to the Altera. Therefore, the latest vendor lock, and choosing a specific FPGA for your project, you automatically select that technical support, documentation, wash the licensed software, the policy of how to apply for support, then.

FPGA most often zastosovuyut at zavdannyah, deyaki deyaki want to significantly speed up the calculation, realizing them at the gate. For example, FPGAs are widely used in the field of signal processing, say, in oscilloscopes, spectrum analyzers, logic analyzers, signal generators, Software Defined Radio and other monitors. Zokrema, LimeSDR vikoristovuetsya Altera Cyclone IV, and in the oscilloscope Rigol DS1054Z cost Xilinx Spartan-6, as well as ProASIC 3 from Actel. More from zastosuvan, about yakі I'm feeling, I can name computer science, recognition of movies and bioinformatics. Є y іnshі projects, development of web servers and DBMS, which work on FPGA. Ale, as far as I know, the whole one is still overflowing with more experimental ones.

Xilinx chi Altera?

It seems that the best Linux is the same one as your well-known Linux guru.

My well-known FPGA guru, especially Dmitry Oleksyuk, has pleased almost all of the Arty Artix-7 development boards from Digilent. FPGA, which wins in it, is Artix-7 in Xilinx. Digilent itself does not offer delivery to Russia, but it is available on AliExpress if you want and with a special nationality (the official price is $ 99). You can also sell yoga on eBay. It’s worth paying a hard fee, but, however, you need a whole lot of adequate pennies.

fun fact! If you just want to program on Verilog or VHDL, it seems strictly that you don’t need to buy an FPGA board. On the back, you can surround yourself with a simulator, the robot will be looked at from afar.

W tsіkavih idiosyncrasies The payment can be called the expansion of sockets in the same way with Arduino-shields. Also, the kit with the board has a tab, for which you can take away the license for Vivado, which shows all the possibilities. The license is valid for one day from the moment of activation, and is also bound to one computer per OS and MAC address.

Upon delivery. I feel that FPGA attachments on board have a great chance of not passing the test. The store on AliExpress, sent to any other country, delivers payments to Russia through the courier service of the SPSR. For the passage of the mitnitsa, it is necessary to fill out an online form with passport data (only data, without photo) and contact phone How can we help more precisely Russian legislation. The next day the payment was delivered by the courier to the door without any food.

Installed Vivado

The Vivado distribution environment is available for purchase at the Xilinx website. Be mentally prepared before you have to go through the registration and fill in the report form for yourself before the bidding. Archived under the name Vivado HLx 2017.2: All OS installer Single-File Download. Do not confuse the vipadkovo with the alleged Vivado Lab Solutions, because they are not the ones you need. The archive should be over 20 GB, so be patient.

Unpacking the archives, launching the installer. We put Vivado HL System Edition. The new version of the loan is on a 47 GB disk. I especially unchecked the Software Development Kit checkbox and filled in the support for only 7 Series add-ons, which changed the size to 12 GB. Jumping a few steps ahead, I will say that such a configuration turned out to be quite sufficient.

Before launching Vivado, it is necessary to add Arty Artix-7 to a new support, because I don’t know anything about this board out of the box. Rumble like this:

cd ~/ opt/ xilinx/ Vivado/ 2017.2 / data/ boards/ board_files
wget https:// github.com/ Digilent/ vivado-boards/ archive/ master.zip
unzip master.zip
mv vivado-boards-master/new/board_files/*./
rm -r vivado-boards-master
rmmaster.zip

Also, take the Arty_Master.xdc file somewhere. Wine is needed further. The file contains a description of light sources, switches, and so on. It will not be easy to blink with light diodes on Verilog without a new one.

First project on SystemVerilog

Vivado says File → New Project ... As the project type, select RTL Project, check the box Do not specify sources at this time. For dialos, the choice of payment type is known in the Arty list.

We are going to add to the project proposals before the XDC file. Copy yoga to the catalog from the project. Then we say File → Add Sources… → Add or create constraints → Add Files, we know a copy of the file, or Finish. The file tree of the project (Sources) of the Constraints group will have the file Arty_Master.xdc, otherwise the copy was named there. You can see and comment on all the rows in the groups Clock signal, Switches and LEDs.

Next we say File → Add Sources… → Add or create design sources → Create File. For the file type, select SystemVerilog, in the file name, enter the letter hello. We say Finish. Next, the Define Module dialog appears, which prompts you to click on the module interface. Dialogue to finish the mark, to those who are the most successful in writing directly in the code, so embossed Cancel.

At the tree of vih_dniki we know new file hello.sv, will be with the Design Sources group. Let's see and write the following code:

`timescale 1ns/1ps

module hello(
input logic CLK100MHZ,
input logic [3:0] sw,
output logic [ 3 : 0 ] led
) ;

always@(posedge CLK100MHZ)
begin
if (sw[0] == 0)
begin
led<= 4"b0001 ;
end
else
begin
led<= 4"b0000 ;
end
end

endmodule

If everything was broken up correctly, at which stage of Vivado you will look like this (clickable, PNG, 71 Kb):

Program compilation takes place in two stages - synthesis and implementation. At the synthesis stage, the program is translated into an abstract language from logic gates and other elements. At the stage of implementation, decisions are made about how to sew this lancet on a specific lash.

Run the synthesis by saying Flow → Run Synthesis or by simply pressing F11. At the top right corner, you will see an indication that the process is running. It may take you a lot of time to do it, depending on your computer and the complexity of the programs. On my laptop, the synthesis induced by the other program took about ten seconds in 10. Now to say Flow → Open Synthesized Design, then you can make a picture like this:

The hour has come to flash our board. We say Flow → Run Imlementation, then Flow → Generate Bitstream. We connect the board to the computer via USB, Vivado says Flow → Open Hardware Manager → Open target → Auto Connect → Program device. You need to specify the path to the bit-file. My vin is like this:

./first-project.runs/impl_1/hello.bit

We say Program. Now the LD4 light is on on the board, which means that the switch SW0 of the omissions is on (div. I'll show you a photo of the board). As if the switch was lifted, the light should not burn. Simply, obviously, but “hello, world”, what did you get? :)

simulation

Simulation is a virtual version of code on Verilog or VHDL directly on your computer, without any PLICIT. This is an hourly and flexible tool, and a framework for covering the code with tests.

When I knew the simulation first, what I had revealed, there were those who didn’t work out. The logs had a simple:

ERROR: Skipped before compiling generated C file [...]xsim_1.c.

Google z cієї pardon knowing only be a nієїnіtnitsa in the style of “try turning on the antivirus”. In the result, the problem was solved by adding the ensign -v 2 to the script ~/opt/xilinx/Vivado/2017.2/bin/xelab. I’ll help you to know that Clang, the binary of such a Vivado, is pulling after you, falling with such mercy:

/a/long/path/to/clang: error while loading shared libraries:
libncurses.so.5: cannot open shared object file: No such file or
directory

And this pardon is already described on the Arch Wiki. Especially, I just copied the reference file from the Vivado_HLS directory:

cp ~/opt/xilinx/Vivado_HLS/2017.2/lnx64/tools/gdb_v7_2/libncurses.so.5\
~/opt/xilinx/Vivado/2017.2/lib/lnx64.o/libncurses.so.5

... after what everything worked out. Otzhe, now, vlasne, an example of a simulation.

By analogy with this, as we created hello.sv, we create a new file hello_sim.sv in the Simulation Sources group. We write the next code for the file:

`timescale 1ns/1ps

module hello_sim();
logic clck_t;
logic[3:0] sw_t;
logic[3:0] led_t;

hello hello_t(clck_t, sw_t, led_t);

initial begin
clck_t<= 0 ;
sw_t<= 4"b0000 ; # 1 ; clck_t <= 1 ; # 1 ; clck_t <= 0 ; # 1 ;
assert(led_t === 4"b0001);

Sw_t<= 4"b0001 ; # 1 ; clck_t <= 1 ; # 1 ; clck_t <= 0 ; # 1 ;
assert(led_t === 4"b0000);
end

endmodule

Right click on the file in the tree view, select Source Node Properties. In the Used In section, check the Synthesis and Implementation checkboxes. Well, I don’t want to, if the testers there made a mockery of our far from human FPGA?

Now we say Flow → Run Simulation → Run Behavioral Simulation. As a result, you will get something like this plan:

You can bachiti, if sw is equal to zero, led is equal to one and navpak. At this point, all changes occur at the front of the clock signal. It looks like the program is working correctly. Well, nothing fell on the assertions, no matter what.

Visnovok

The archive with the project described above can be obtained. As an additional source of information, I recommend bi steps:

• Like you to chirp the details of the hall, to give respect to

PROJECT IMPLEMENTATION ON FPGA

Following the development of a logical scheme with different functional models, it is necessary to place it on a crystal. Then we will model the circuit with the improvement of the actual fittings of the elements, taken away after the placement of the circuit on the crystal. If necessary, correct the solution. If there is a reason for the scheme to be entangled in the PLIS, then it is put into practice on the stand.

Rice. 82. Stages of designing a digital add-on on PLIS

Main stages of FPGA design (with lectures):

The layout of the attachment is being developed and entered into XILINX.

IMPLEMENTATION is victorious (broadcasting, shaping the scheme with a path of library elements, optimization, placement on a crystal).

Programming.

1. Associative memory. Organization, method of selection, on the vіdmіnu vіd address za.

Associative access implement the search for information for a certain sign, and not for її roztashuvannyam in memory (with an address or a missive in the heart). In the most recent version, all the words that are stored in the memory are immediately converted to distinguishable signs, for example, to the zbіg sing fields of words (tags - like the English word tag) with the sign that is given by the input word (tag address). Words are seen on the outside, they seem to give a sign. The discipline of writing words, as well as the discipline of recording new data, can be different. The main area of ​​associative memory retention in modern EOM is memory of data.

In associative attachments, which are remembered, the search for information is carried out behind an associative sign, recorded in the skin of the memory box.

At the register of the mask, a word is written, which allows you to ask for everything, or even with some associative signs, zastosuvannya mask allows you to speed up or expand the area of ​​​​the search.

The search for information is carried out in parallel along all the middle paths in line with the associative sign of the skin center.

The result of the search is a special combination scheme that vibrates signals, that tells about the number of words, that satisfies the minds with a joke, about the presence of only one word, about the presence of a few words, which may have such an associative sign.

After the formation and processing of the notification signals, the control circuit will read the necessary information. When recording, I know the correct middle for the employment category, in the first I found the right middle for recording information.

Rechecking the employment category is carried out at the time of the installation of the n-th category (employment category) of the mask. When varying additional combinational schemes in associative memory, it is possible to select different logical operations, choosing the maximum and minimum number, the number of words, which can be the same associative sign only. The middle memory of the associative attachment is due to elements of static memory, in the associative memory the memory is carried out until all the middles at once and it is not guilty to be interrupted by regeneration cycles. Associative memory is the most common, but even more expensive, because it requires the introduction of an additional scheme of alignment, which allows you to send a request for skin middle memory. Therefore, such a memory does not ring out in a pure look, but a fast-moving memory like Kesh sounds like a partly associative one.

ATmore associative cache memory (FACM, Fully Associated Cache Memory), the skin of the middle takes data, and the "tag" field - the full physical address of the information, a copy of which is recorded. In case of any exchanges, the physical address of the information that is being requested is compared with the "tag" fields of all the middles, and when the number is changed, the Hit signal is set to the middle.

When reading and the value of the signal Hit = 1, the data is sent to the data bus, because there is no memory (Hit = 0), then when reading from the main memory, the data together with the address are placed at the address, or else, which has not been read for a long time, cache-memory 'yati.

When writing data at once with the address of the folder, as a rule, they are placed in the cache memory (the folder is shown when Hit = 1 and is not valid when Hit = 0). The copying of data into the main memory is consummated under the supervision of a special controller, if there is no memory to memory.

Memory type FACM є even foldable extensions and vikoristovuєtsya only for small spaces, the main rank of special additions. At the same time, this type of cache memory provides the most functional flexibility and conflict-free address, so that if only one piece of information can be captured in a cache-memory combo.

3 lectures:

Associative extensions to remember

The principle authority is those that the system of information selection from them is established not for the unique address of the information, but for the sign, as a matter of fact, part of the shukano information.

The tag is a symbol of the mark, for the zbіg z yakim, there is a piece of information.

The scheme of the associative RFP has been simplified:

Storage zone - address memory with numbered middles, collecting information and tags.

For retrieval to the associative memory of the register, the letter of the joke tag is removed. Payment scheme The zbіg is installed on the zbіgіv register, de zbіg tag from the memory from the clear. Possible reactions (not enough zbіgіv; є wanting only one zbіg - for this type of knowledge, the center of knowledge should be placed in the register of data; multiple zbіg - the COP can take a decision, as a result, it is enough for processing).

Zastosuvannya: DB, basic knowledge, PC yak cache.

It should be noted that the processor replaces the need to complete the first set of instructions, re-apply the skin program and rewrite the algorithm directly to the “salize”. This is how you practice FPG. In today’s article, I’ll tell you how it’s possible, and I’ll let you know about different FPGA design methods.

For the cob it is necessary to understand the digital logic of ASIC microchip robots, but to start with them is more complicated and expensive, and it is shorter to start with FPGA.

What is FPGA?

FPGA deciphered as a field-programmable gate array (programmable gate array, FPGA). The stench is called PLIS - programming logical integrated circuits.

For the help of FPGA, you can literally design digital microcircuits, sitting at home with an affordable salary on the table and software retailer for a thousand green rubles. Ale and bezkoshtovnі options. To give respect: to design it yourself, not to program it, to that at the end we take a physical digital circuit, which will build the song algorithm on a hardware level, and not a program for a robot.

Practice in this way. A board with a set of interfaces is ready, so that it is connected to the FPGA microcircuit installed on the board, such a cool board for the data center, or as a tax payment for training.

Until we achieve FPGA, there is simply no logic in the middle of the microcircuit for processing data from interfaces, and there will be nothing to work on, obviously. Ale, as a result of the design, a firmware will be created, as soon as the FPGA is conceived to create the necessary digital circuit. In this way, you can create a 100G Ethernet controller, which will be able to process the meshed packets.

An important feature of FPGA is the ability to reconfigure. It is permissible for us to need a 100G Ethernet controller at a time, and after a while the board itself can be tested for the implementation of some independent 25G Ethernet interfaces.

There are two leaders in the FPGA-chip manufacturer on the market: Intel and Xilinx. The stench controls 58 and 42% of the market. The first of our FPGA chips, the founders of Xilinx, was born in 1985. Intel came to the market quite recently - in 2015, the company, having ditched Altera, was founded at the same time as Xilinx. The technologies of Altera and Xilinx are very similar in many respects, as they are the middle of development. Most of the time I've worked with Xilinx products, so don't be surprised at the post's post.

FPGA is widely used in various areas: electronics, telecommunications, storage boards for data centers, robotics, ASIC prototyping. I will sort out the troch below.

Let's take a look at the technology that ensures hardware reconfiguration, learn from the design process and find a simple example of implementing my Verilog hardware device. If you have a custom FPGA board, you can repeat it yourself. If you don’t have to pay, then you can still learn Verilog by simulating the circuits on your computer.

Working principle of FPGA

The FPGA chip is the same ASIC chip itself, which is made up of the same transistors, from which the triggers, registers, multiplexers and other logic elements for the largest circuits are selected. It is obviously not possible to change the order of connection of these transistors. But architecturally, the microcircuit was inspired by such a cunning trick that it is possible to change the switching of signals between larger blocks: they are called CLB - programming logic blocks.

You can also change the logical function, like overriding CLB. Reaches tse zavdyaki to the fact that the entire microcircuit is permeated with the cores of the Static RAM configuration memory. The skin bit of the memory either controls the signal switching key, or the partial truth table of the logical function that implements the CLB.

Since the configuration memory is induced by the Static RAM technology, then, first, when the FPGA live is enabled, the language chip needs to be configured, and in another way, the microcircuit can be reconfigured a number of times.

The CLB blocks are located in the switching matrix, as a function of the inputs and outputs of the CLB blocks.

There are six keys on the dermal web of the conductors, which flicker, keratinized by their configuration memory cores. With one curve or another, it is possible to ensure different switching of signals between CLB.

CLB is simply stacked in a block that defines a Boolean function with a number of arguments (it's called a Look Up Table, LUT) and a trigger (flip-flop, FF). Modern FPGA LUTs have six inputs, but for simplicity, three are shown for simplicity. The LUT output is applied to the CLB output either asynchronously (without a middle), or synchronously (via the FF trigger, which works at the system clock frequency).

Tsіkavo marvel at the principle of implementation LUT. Let us have a function Boolean y = (a & b) | ~ c. Її circuit design and truth table shows a little. The function has three arguments, so there are 2^3 = 8 values. The skin of them allows combinations of input signals. Values ​​are calculated by the FPGA firmware expansion program and recorded in a special configuration memory.

The skin value of the middle value is fed into the output of the LUT multiplexer, and the input arguments of the Boolean function are selected to select the other value of the function. CLB is the most important FPGA hardware resource. The amount of CLB in today's FPGA crystals can be different and occur depending on the type and capacity of the crystal. Xilinx may have crystals with a quantity of CLB between approximately four thousand to three million.

Crim CLB, middle FPGA is still low important hardware resources. For example, hardware blocks are multiple of accumulated or DSP blocks. The skin of them can be used to multiply and fold 18-bit numbers of the skin cycle. For top crystals, the number of DSP blocks can exceed 6000.

The second resource is all blocks of internal memory (Block RAM, BRAM). The skin block can save 2 KB. Povna єmnіst such a memory, fallow in the crystal, can reach from 20 Kbytes to 20 Mbytes. Like CLB, BRAM and DSP-blocks are connected by a switching matrix and permeate the entire crystal. By linking the CLB, DSP and BRAM blocks, even more efficient data processing schemes can be used.

FPGA Advantages

The first FPGA chip, created by Xilinx in 1985, has more than 64 CLBs. At that time, the integration of transistors on microcircuits was richly lower, lower at a time, and in digital devices, microcircuits of “loose logic” were often victorious. There were also microcircuits of registers, lichilniks, multiplexers, multipliers. Specifically, the attachments were created by their own board, where low-integration microcircuits were installed.

Wikoristannya FPGA allowed to follow this approach. Navit FPGA on 64 CLB significantly save space on other boards, and the availability of reconfiguration made it possible to upgrade the functionality of attachments after preparation for an hour of operation, as it seems “in the field” (name and name - field-programmable gate array).

For the reason that in the middle of the FPGA it is possible to create a hardware digital circuit (the most important thing is to get resources), one of the most important PLIC projects is the prototyping of ASIC chips.

The development of ASIC is more complicated and expensive, the price of pardon is even higher, and the power of testing the logic is critical. Therefore, one of the stages of the development of work on the physical topology of the circuit to the beginning was її prototyping on one or more FPGA crystals.

For ASIC expansion, special boards are issued to cover a lot of FPGAs connected to each other. The prototype of the microcircuit works at significantly lower frequencies (perhaps tens of megahertz), but it also allows you to save on the identified problems and bugs.

However, in my opinion, іsnuyut cіkavіshi zastosuvannya PLIS. The flexible structure of the FPGA allows the implementation of hardware circuits for high-width and parallel processing of data with the ability to change the algorithm.

Let's think about what the CPU, GPU, FPGA and ASIC are fundamentally. The CPU is universal, on it you can run any algorithm, the most flexible one, and make it easier to achieve a great number of programs and middleware.

In this case, through the versatility and the last of the CPU instructions, the productivity decreases and the power supply of the circuit increases. It is worth noting that on the skin of the arithmetic operation of the CPU there are a lot of additional operations related to reading instructions, moving data between registers and cache and other body changes.

On the other side there is an ASIC. On this platform, the required algorithm is implemented in hardware for a direct connection of transistors, all operations are related only to the algorithm and there is no possibility to change it. See the maximum productivity for the least energy efficient platform. And the ASIC axis cannot be reprogrammed.

On the right side of the CPU is the GPU. The microcircuits were split up in order for processing graphics, but at the same time they were hacked and for mining, calculating the main feature. The stench is composed of thousands of small counting nuclei and counting in parallel operations on an array of data.

If the algorithm can be parallelized, then on the GPU you can reach a significant speedup compared to the CPU. On the other hand, the following algorithms are implemented faster, so the platform appears less flexible, lower CPU. Also, for the development of a GPU, you need a mother of special skills, knowledge of OpenCL and CUDA.

Zreshtoy, FPGA. This platform will improve ASIC efficiency due to the ability to change the program. PLIS is not universal, but it uses a class of algorithms and tasks, so that they can show better productivity, lower on the CPU and on the GPU. Foldability of distribution for FPGA is more, prote novі zasobi rozrobki rozroby tsei rozryv smaller.

The critical point of FPGA is the need to process data at the pace of your choice with minimal delay in response. As an example, you can reveal a smart interfacing router with a large number of ports: if you need an Ethernet packet on one of the ports, you need to reverse the anonymous rules, first choose the outgoing port. It is possible, if necessary, to change the actual fields of the package or add new ones.

The FPGA variant allows the task to be changed: the bytes of the packet just started to enter the microcircuit of the media interface, and its header is already being analyzed. The choice of processors here can significantly increase the speed of processing the traffic. It is clear that the recommended ASIC chip can be used for routers, which is the most efficient way, but why should the packet processing rules be changed? Achieve the necessary flexibility in the future with high productivity to help only FPGA.

In this rank, FPGA wins there, de needing high data processing productivity, the least hour of reaction, and also low power consumption.

FPGA in the cloud

In gloomy FPGA billings, there is a need for a quick account, speeding up traffic and access to data arrays. Here you can see the FPGA switchboard for high-frequency trading on exchanges. At the server, FPGA boards with PCI Express and an optical interface of Intel (Altera) or Xilinx are inserted.

Cryptographic algorithms directly affect FPGA, aligning DNA sequences and scientific tasks with the molecular dynamics landscape. Microsoft has long been winning FPGAs for speeding up the Bing jockey service, as well as for organizing Software Defined Networking in the middle of Azure.

The boom in machine learning is not bypassing the FPGA. Xilinx and Intel are proposing FPGA-based chips to work with deep neurotransmitters. They allow you to use FPGA firmware, so that you can implement the same thing without intermediary frameworks for Caffe and TensorFlow.

Moreover, you can try everything without leaving the house and vicorist gloomy services. For example, Amazon can rent a virtual machine with access to the FPGA board and any kind of development tools, including machine learning.

FPGA on the edge

What else can a cicada work on FPGA? That scho does not shy away! Robotics, unmanned vehicles, drones, scientific gadgets, medical equipment, corystuval mobile attachments, smart video surveillance cameras, etc.

Traditionally, FPGAs were used for digital processing of single-mode signals (and competed with DSP processors) in radar attachments, receiving radio signals. With the increasing integration of microcircuits and the increased productivity of the FPGA platform, there has become more and more stagnant for high-performance calculations, for example, the processing of two-world signals "on the edge of the gloom" (edge ​​computing).

This concept is easier to understand on the basis of a video camera for analyzing car traffic with the function of recognizing car numbers. You can take a camera with the ability to transmit video via Ethernet and process it on a remote server. With the increase in the number of cameras, there will be an increase in the number of cameras, which can lead to a system failure.

It is more efficient to implement the recognition of numbers on the encoder installed directly into the body of the video camera, and transfer the numbers of cars in the dark to the text format. For this purpose, you can take equally inexpensive FPGAs with low power consumption to get by with a battery. With this, it becomes impossible to change the logic of the FPGA robot, for example, when changing the standard of car numbers.

When it comes to robotics and drones, then in this sphere it is especially important to win over two minds - high productivity and low energy. The FPGA platform is more suitable and can be more victorious, zocrema, for the creation of field controllers for drones. Already at the same time roar UAVs, as they can praise the solution for a lot.

Development of the project on FPGA

Іsnuyet raznі іvnі design: low, block and high. A low level of transfer of the most common types to the Verilog type or VHDL, which you can use only on register transfer levels (RTL - register transfer level). In this way you form registers, like a processor, you designate logical functions that change data between them.

FPGA circuits always operate at the highest clock speeds (100-300 MHz), and at equal RTL you determine the behavior of the circuit to the exact clock of the system frequency. This little bit of work is done to create the most efficient schemes in terms of productivity, resource reduction of the FPGA crystal and energy saving. But here you need serious skills in circuitry, and with them the process is non-standard.

On the block level, you are more importantly involved in the development of great blocks, which are already ready, as if they were singling out functions, for the removal of the system-on-chip functionality you need.

On a high level of design, and no longer control data on skin tact, we concentrate on algorithms. Use compilers or translators to convert C and C++ to RTL, for example Vivado HLS. Vіn dosit razumny that allows translyuvati on the hardware level a wide class of algorithms.

The main problem of such an approach before RTL movs is speeding up the development and especially testing of the algorithm: the C ++ code can be run and verified on a computer, and it will be richer, lower testing, change the algorithm on the RTL level. For zruchnіst, zvichayno, you have to pay - the scheme can be not so fast and borrow more hardware resources.

Often, we are ready to pay the price: to correctly tweak the translator, the efficiency does not suffer much, and the resources of modern FPGAs are sufficient. In the world with the critical indicator of time to market, it appears to be true.

Often in one design it is necessary to combine all three styles of design. Let's say we need to build attachments, which we could put into a robot and give it to the building to recognize objects in video streams - for example, road signs. Let's take a video sensor chip and connect directly to the FPGA. For customization, we can use an HDMI monitor, as well as connections to FPGA.

Frames from the camera will be transferred to the FPGA via an interface, which is predetermined by the sensor picker (USB is not an issue here), processed and displayed on the monitor. To process frames, you need a framebuffer, which sound is found in the original DDR memory, installed on another board in the order of the FPGA chip.

Since the video sensor maker does not provide Interface IP for our FPGA chip, we have to write our own RTL, depending on the clock, bit and bit, depending on the specification of the data transfer protocol. Blocks Preprocess, DDR Controller and HDMI IP mi, better for everything, take it easy and just get their interface. And the HLS block, which looks like a search and data processing, we can write in C++ and translate Vivado HLS for help.

Above all, we will still need the library of the detector and the classifier of road signs, adapted for the FPGA version, to be ready. For this application, I, obviously, have a very simplified flowchart for design, but the logic of the robot does not appear correctly.

Let's take a look at the design path from writing the RTL code to the creation of a configuration file for FPGA capture.

Then, you write the RTL code that implements the schema you need. First of all, you need to reconsider on a real basis, you need to reconsider, which is correct and correct the necessary order. For whom the RTL-modeling is done on the simulator on the computer.

You take your circuit, presented only in RTL code for the time being, and place it on a virtual stand, send sequences of digital signals to the inputs of the circuit, register the outputs with diagrams, and check the results of the inputs on the hour. Sound you know the pardons that turn until the RTL is written.

Dali logically verifications the code is sent to the input to the program-synthesizer. She's converting the text description of the circuit into a list of digital elements from the library available for this FPGA chip. This list will have such elements as LUT, triggers and links between them. At this stage, the elements are still not tied to specific hardware resources. To do this, you need to apply Constraints on the circuit - a zocrema, for example, with some physical contacts of the input-visualization of the FPGA microcircuit for the logical input of your circuit.

In these exchanges, it is also necessary to indicate which clock frequencies the circuit is to blame for. The output of the synthesizer and the file is given to the Processor Implementation, which, moreover, takes care of the placement and routing (Place and Route).

The process Place the skin docks of the netlist element binds to a specific element in the middle of the FPGA chip. Then we start the Route process, which tries to know the optimal configuration of these elements for a specific configuration of the PLIC switching matrix.

Place and Route are running out of the border, overlaid by us on the circuit: input-output contacts and clock frequency. The period of the clock frequency even strongly influences the Implementation: the fault is not to blame for the smaller, lower clock delay on the logical elements of the critical lance between the two last triggers.

Often, I can’t help but be satisfied, and then I need to turn to the first stage and change the RTL code: for example, try to speed up the logic in critical language. After the successful completion of the Implementation, we know how the elements are known and how the stench is caused.

Just a little later, the process of creating a binary file of the FPGA firmware. Lost yoga zavantazhit in real zalizo and reverify, chi wono pratsyuє so, like ochіkuvalos. How many stages blame the problems, henceforth, the modeling was inaccurate and how many stages were used all the pardons and shortcomings.

You can turn to the stage of simulation and simulate a random situation, but even if you don’t, you can go to the extreme point of transferring the mechanism of improvement without a hitch in the hall, which works. You can specify which signals you want to see in the hour, and the middle of the analysis generates an additional logic analyzer circuit, so that the order is placed on the crystal with your circuit, connected to the signals, which you chirp, and take the hourly value. Saving hours by diagrams of required signals can be done on a computer and analyzed.

VICORISTANNY PLIS AT SUCHASHNYh ATTRACTIONS

Tupikov Pavlo Andriyovich

5th year student, Department of Art OmDTU, Russian Federation, m. Omsk

On this day, the programming of logic integrated circuits (PLICs) is becoming more and more crowded at various modern outbuildings, which is due to the fact that PLICs may have significant advantages due to the most powerful digital microcircuits. Before these advances can be seen:

· Pokraschuyusya watch characteristics virobu.

· The price changes.

· Changing the dimensions of the viroba.

· Changes in the number of discrete microcircuits (the number of discrete microcircuits changes)

· Moves the flexibility of the vibration (PLIS can always be reprogrammed)

PLIS architecture can be folded (Fig. 1)

Figure 1. FPGA internal structure

As you can see from the little one, the main part of the PLIS is composed of programming logical blocks and programming internal links.

The very process of programming (firmware) PLIS is used for molding the necessary connections between inputs and outputs.

On this day, the world has two leaders of the world at the forefront of PLIS. All American firms Xilinx and Altera.

The leather company promotes its own CAD for FPGA robots. Xilinx promotes the Xilinx Software Development Kit (SDK). Altera promotes Max+Plus II and Quartus II, as well as the ModelSim simulation system.

For the creation of firmware programs, ring out the movie description of the robotic equipment, the most widened for today, the widest such movi:

Verilog HDL.

Mova VHDL є Nab_lsh is a folding for inhibitory, Ale with Cyoma Mait Nabіlshі Mozhvyosti on the functions of the Oblogii, one but Menshі Mozhvyosti on the structural R_VNI Abstsіji, pivotno z Verilog HDL, for the robustness of Movy VHDL BULL-VITAL BLIBLINE VITAL (MAL. 2).

Figure 2. Equal abstractions Verilog і VHDL

The butt of the Verilog HDL robot is a program implemented on the PLIC CYCLONE III EP3C5E1444C8N of the Mini-DiLab stand, a brilliant look of such representations in fig. 3.

Figure 3 Mini - DiLab

This program implements the subsequent switching of the led0-led7 lights, with the choice of increasing the “vognik” movement for the additional buttons pba and pbb, as well as the control of the switching for the additional switches sw0, sw1.

//Program text

module project( output led, input clk_25mhz, input pba, input pbb,

input sw);

// Assignment of internal documents to the project

wire s1;

wire s2;

wire s3;

// Call for other files (subprogram) that are connected to the project

Tr tr_1 (.out(s2), .set(pba), .res(pbb));

Counter counter_1 (.q(s1), .clk(clk_25mhz), .up(s2));

Mx mx_1 (.a(s3), .in(s1), .load(sw));

Dc3_8 dc3_8_1 (.out(led), .in(s3));

endmodule// end of program

Subprogram tr

module tr(out, set, res); // Program creation

// Assignment of inputs/visnovkіv

outputreg out;

input set;

input res;

// Initialization

initial

begin

out<= 1"d0;

// Main program code

always @(negedge set or negedge res)

begin

if(~(set))

out<= 1"d1;

else

out<= 1"d0;

endmodule // End of the program

Subprogram counter

module counter(con, q, clk, up); // Cob program

outputreg con;

output q = con;

input up, clk;

// Main program code

always @(posedge clk)

begin

if(clk)

if(up)

Con<= con - 1"d1;

else

Con<= con + 1"d1;

endmodule//Kіnets program

Subprogram mx (multiplexer)

module mx( output.reg a, input in, input load);

// Main program code

always @*

begin

case(load)

2"b00: a = in;

2"b01: a = in;

2"b10: a = in;

2"b11: a = in;

endcase

endmodule // End of the program

Subprogram dc3_8 (multiplexer)

module dc3_8(out, in); // Cob program

// Assigning inputs/outputs

output.reg out;

input wire in;

// Main program code

always @*

begin

case(in)

3"d0: out = 8"b11111110;

3"d1: out = 8"b11111101;

3"d2: out = 8"b11111011;

3"d3: out = 8"b11110111;

3"d4: out = 8"b11101111;

3"d5: out = 8"b11011111;

3"d6: out = 8"b10111111;

3"d7: out = 8"b01111111;

endcase

endmodule // End of the program

The program was implemented by CAD Quartus II.

After compiling the program, the compiler has not seen a pardon that is respected by the program, due to the analysis and syntax of the program (Fig. 4).

Figure 4. Project summary window

It is respected by the compiler to talk about the number of licenses for Quartus II (there was a free version of the program for learning) and the number of files necessary for modeling the project.

The structure of this project is shown in Fig. 5.

Figure 5. Implementation of the project ( RTL structure)

Yak is shown in fig. 6 in this program, there is only an insignificant part of the possibilities of this PLIS.

Figure 6. Part of the FPGA that takes part in the robot project

Visnovki: Programming logical integrated circuits can be stuck in the accessories. To learn the work with them, they should be introduced into the program of specialties related to the design and construction of radio-electronic equipment, familiarity with the description of the equipment (Verilog HDL and VHDL).

List of literature:

1. Grushevitskiy R.I. Designing systems based on program logic microcircuits / R.I. Hrushevitsky, A.Kh. Mursaev, E.P. Frowning. St. Petersburg: BHV Petersburg, 2002. - 608 p.

2. Kolomov D.A. Computer-aided design systems from Altra MAX+plus II and Quartus II. A short description of the self-reader / D.A. Kolomov, R.A. Myalk, A.A. Zobenko, O.S. Pylypiv. M: IP RadioSoft, 2002. - 126 p.

3. Maxfield K. PLIS design. The course of a young soldier. / K. Maxfield. M.: Vydavnichy dіm "Dodeka-XXI", 2007. - 408 p. (Translated from English).